Phase interpolation circuit, reception circuit, and semiconductor integrated circuit
US12081219B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 16, 2023 |
| Grant date | Sep 3, 2024 |
| Priority date | — |
| Expiry date | May 16, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/03057
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase interpolation circuit includes: a first buffer circuit configured to adjust a rise time or a fall time of a first reference clock signal based on a first control signal to generate a first input clock signal; a second buffer circuit configured to adjust a rise time or a fall time of a second reference clock signal based on a second control signal to generate a second input clock signal; a detection circuit configured to detect a rise time or a fall time of the first input clock signal or the second input clock signal and generate the first control signal and the second control signal according to a detection result thereof; and a mixer circuit configured to generate an output clock signal having a phase between a phase of the first input clock signal and a phase of the second input clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.