Common-mode current removal schemes for digital-to-analog converters
US12081229B2 · kind B2 · utility
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26Claims
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Key dates
| Filing date | Jul 11, 2022 |
| Grant date | Sep 3, 2024 |
| Priority date | — |
| Expiry date | Dec 14, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/785
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Methods and apparatus for common-mode current removal in a digital-to-analog converter (DAC). An example DAC circuit generally includes a plurality of current-steering cells, a resistor ladder circuit coupled to the plurality of current-steering cells and having a plurality of shunt branches, and an adjustable resistance circuit coupled between middle nodes of the plurality of shunt branches and a reference potential node for the DAC circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.