Low power switch
US12081434B1 · kind B1 · utility
0Cited by
4References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 30, 2021 |
| Grant date | Sep 3, 2024 |
| Priority date | — |
| Expiry date | Mar 9, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/109
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A data plane integrated circuit that includes interfacing units (IFUs), Datapath units (DPUs); and a network on chip (NoC). The DPUs are arranged in local sets of DPUs that are proximate to each other, each local set is configured to (a) store an instance of packet header processing control data structures and (b) independently perform local packet header processing and transmission scheduling.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.