Reading circuit for a pixel array
US12081888B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 21, 2022 |
| Grant date | Sep 3, 2024 |
| Priority date | — |
| Expiry date | Jun 4, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N25/677
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to a read-out circuit comprising N inputs configured to be connected to N respective outputs of a pixel array of an image sensor, with N being an integer strictly greater than 1; and N analog-to-digital converters organized in K groups, with K being an integer strictly greater than 1 and strictly less than N, and each having a first input coupled to a respective one of the N inputs and a second input. In each group, the second inputs of the analog-to-digital converters of the group are connected together, electrically decoupled from the second inputs of the analog-to-digital converters of the other groups, and configured to receive a first reference signal that is identical for all the analog-to-digital converters of the group.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.