Method for manufacturing memory and memory
US12082393B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 6, 2021 |
| Grant date | Sep 3, 2024 |
| Priority date | — |
| Expiry date | Apr 12, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/50
Abstract
A method for manufacturing a memory and a memory is provided. The method for manufacturing a memory includes: providing a substrate; stacking an electrode support structure, a protective layer and a first mask layer in sequence on the substrate; patterning the first mask layer on an array region, and etching the protective layer, the electrode support structure and the substrate by using the patterned first mask layer as a mask, to form capacitor holes penetrating the protective layer and the electrode support structure and extending into the substrate; removing the first mask layer; and forming a first electrode layer on side walls and bottom walls of the capacitor holes, a top surface of the first electrode layer being flush with a top surface of the electrode support structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.