Anti-fuse readout circuit, anti-fuse memory, and testing method
US12082402B2 · kind B2 · utility
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22Claims
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Inventor
Key dates
| Filing date | May 30, 2022 |
| Grant date | Sep 3, 2024 |
| Priority date | — |
| Expiry date | Jan 6, 2043 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An anti-fuse readout circuit, an anti-fuse memory, and a testing method are provided. The anti-fuse readout circuit includes: a latch circuit configured to latch data read out from an anti-fuse storage array; and a transmission circuit connected to an output terminal of the latch circuit, the transmission circuit being configured to transmit data latched in the latch circuit to a data port in response to a read test command.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.