Three-dimensional semiconductor memory device with vertical structures between contact plugs
US12082412B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 21, 2021 |
| Grant date | Sep 3, 2024 |
| Priority date | — |
| Expiry date | Sep 8, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/50
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A three-dimensional semiconductor memory device includes a substrate including a cell array region and a connection region, an electrode structure including electrodes vertically stacked on the substrate, the electrodes including pad portions on the connection region, respectively, and the pad portions of the electrodes being stacked in a staircase structure, first vertical structures penetrating the electrode structure on the cell array region, and second vertical structures penetrating the electrode structure on the connection region, each of the second vertical structures including first parts spaced apart from each other in a first direction, and at least one second part connecting the first parts to each other, the at least one second part penetrating sidewalls of the pad portions, respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.