Semiconductor device including blocking pattern, electronic system, and method of forming the same
US12082423B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 24, 2022 |
| Grant date | Sep 3, 2024 |
| Priority date | — |
| Expiry date | Dec 25, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/011
Abstract
A semiconductor device includes a horizontal wiring layer on a substrate, a stack structure disposed on the horizontal wiring layer and including insulating layers and electrode layers alternately stacked on each other, and a pillar structure extending into the horizontal wiring layer and extending through the stack structure. The electrode layers include one or a plurality of selection lines adjacent to an uppermost end of the stack structure, and word lines surrounding the stack structure below the one or plurality of selection lines. The pillar structure includes a variable resistive layer, a channel layer between the variable resistive layer and the stack structure, a gate dielectric layer between the channel layer and the stack structure, and a blocking pattern disposed between the variable resistive layer and the channel layer and being adjacent to a first selection line among the one or plurality of selection lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.