Cache architecture for a massively parallel processing array
US12086066B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 15, 2023 |
| Grant date | Sep 10, 2024 |
| Priority date | — |
| Expiry date | Mar 15, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/154
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A cache architecture for an array of identical cores arranged in a grid. Each of the cores include interconnections to neighboring cores in the grid, a memory, and an algorithmic logic unit. A first core of the array is configured to receive a memory access request for data from at least one core of the array of cores configured to perform a computational operation. A second core of the array is configured to determine whether the requested data is present in a cache memory via a cache index including addresses in the cache memory. A third core of the array is configured as the cache memory. The memory of the third core is used as the cache memory. An address of the requested data from the cache index is passed to the third core to output the requested data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.