Memory vulnerability mitigation
US12086072B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 11, 2020 |
| Grant date | Sep 10, 2024 |
| Priority date | — |
| Expiry date | May 30, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/023
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Vulnerabilities to physical memory, such as server dynamic random access memory (DRAM) with error correction code (ECC) capability, can be mitigated though the use of guard pages allocated in that physical memory. Physical memory pages can be mapped to virtual memory pages of a contiguous virtual address space. When an error such as a bit flip is detected in a physical memory page, the data from that physical memory page can be copied to a protected page, such as a guard page or page isolated from other sensitive data. Information such as an error correction code (ECC) can be used to determine and correct the erroneous bit. The mappings in a related page table can be updated such that the same virtual pages or addresses are then mapped to the guard page that now includes the relevant data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.