Memory management method and electronic device
US12086420B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 6, 2023 |
| Grant date | Sep 10, 2024 |
| Priority date | — |
| Expiry date | Feb 6, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F3/0673
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An electronic device comprises: a memory management module; a processor operatively connected to the memory management module; and a memory controlled by the memory management module and operatively connected to the processor. The memory is configured to store instructions which, when executed, cause the processor to: execute at least one process, identify a rate at which the at least one process is terminated, based on a preconfigured first cycle, determine a number of times the identified rate exceeds a first threshold value, and based on a determination that the number of times the identified rate exceeds the first threshold value is greater than a second threshold value, reboot the electronic device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.