Capability-generating address calculating instruction
US12086593B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 7, 2021 |
| Grant date | Sep 10, 2024 |
| Priority date | — |
| Expiry date | Apr 15, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F21/71
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus has processing circuitry, an instruction decoder, and capability registers, each capability register to store a capability comprising a pointer and constraint metadata for constraining valid use of the pointer/capability. In response to a capability-generating address calculating instruction specifying an offset value, a reference capability register is selected as one of a program counter capability register and a further capability register. A result capability is generated for which the pointer of the result capability indicates a window address identifying a selected window within an address space, the selected window being offset from a reference window by a number of windows determined based on the offset value of the capability-generating address calculating instruction. The reference window comprises the window comprising an address indicated by the pointer of the reference capability register.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.