Patent · US Active

Array processor using programmable per-dimension size values and programmable per-dimension stride values for memory configuration

US12086597B2 · kind B2 · utility

0Cited by

11References

17Claims

0Family size

Assignee

Silicon Laboratories Inc. · US

Inventors

Matthew Brandon Gately · Austin, US
Eric Jonathan Deal · Austin, US
Mark W. Johnson · Vancouver, CA

Key dates

Filing date	Jun 28, 2021
Grant date	Sep 10, 2024
Priority date	—
Expiry date	Jun 28, 2041

Classification

Technology area (CPC G)Physics
CPC primaryG06F9/3455
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

An apparatus includes an array processor to process at least one array. The apparatus further includes a memory coupled to the array processor. The at least one array is stored in memory with programmable per-dimension size and stride values.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.