Software visible and controllable lock-stepping with configurable logical processor granularities
US12086653B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 24, 2020 |
| Grant date | Sep 10, 2024 |
| Priority date | — |
| Expiry date | Dec 17, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/45558
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor is described. The processor includes model specific register space that is visible to software above a BIOS level. The model specific register space is to specify a granularity of a processing entity of a lock-step group. The processor also includes logic circuitry to support dynamic entry/exit of the lock-step group's processing entities to/from lock-step mode including: i) termination of lock-step execution by the processing entities before the program code to be executed in lock-step is fully executed; and, ii) as part of the exit from the lock-step mode, restoration of a state of a shadow processing entity of the processing entities as the state existed before the shadow processing entity entered the lock-step mode and began lock-step execution of the program code.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.