Bias voltage generation circuit for memory devices
US12087384B2 · kind B2 · utility
0Cited by
6References
16Claims
0Family size
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Key dates
| Filing date | Feb 10, 2022 |
| Grant date | Sep 10, 2024 |
| Priority date | — |
| Expiry date | Jul 17, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/26
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to memory devices and, more particularly, to bias voltage generation circuit for memory devices and methods of operation. The voltage generation circuit includes: an internal voltage generator which providing a bias voltage to at least one internal node of a bias voltage generation circuitry; and at least one pre-charging circuitry providing a predefined bias voltage to at least one internal node including a distributed network of local drivers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.