Methods and systems for managing read operation of memory device with single ended read path
US12087387B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 23, 2022 |
| Grant date | Sep 10, 2024 |
| Priority date | — |
| Expiry date | Nov 18, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2281
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes at least one bitcell; read circuitry coupled to the at least one bitcell; and screening circuitry coupled to the read circuitry, wherein the screening circuitry includes a master slave flip-flop configured to store an output of the at least one bitcell during a read operation of the memory device, wherein the master slave flip-flop includes a master latch and a slave latch; and a DOUT window controller coupled to the master slave flip-flop and configured to generate and control a master clock signal for the master latch to determine if the at least one bitcell is a weak bitcell; and generate and control a slave clock signal for the slave latch to enable toggling of the output of the at least one bitcell during a transparent window between the master clock signal and the slave clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.