Packaged integrated device with memory buffer integrated circuit die and memory devices on module substrate
US12087681B2 · kind B2 · utility
0Cited by
29References
20Claims
0Family size
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Key dates
| Filing date | Jul 5, 2023 |
| Grant date | Sep 10, 2024 |
| Priority date | — |
| Expiry date | Jul 5, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/49816
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is an integrated circuit die of a memory buffer integrated circuit that is placed aggregately closer to the solder balls that connect to the input (i.e., host command/address—C/A) signals than the output solder balls (i.e., memory device C/A) signals. This decreases the length of the host C/A signals from the memory controller to the memory buffer device when the memory module is placed in a system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.