Semiconductor package and methods of manufacturing a semiconductor package
US12087717B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 7, 2021 |
| Grant date | Sep 10, 2024 |
| Priority date | — |
| Expiry date | Aug 8, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/13091
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In an embodiment, a semiconductor package includes a first transistor device having first and second opposing surfaces, a first power electrode and a control electrode arranged on the first surface and a second power electrode arranged on the second surface. A first metallization structure arranged on the first surface includes a plurality of outer contact pads which includes a protective layer of solder, Ag or Sn. A second metallization structure is arranged on the second surface. A conductive connection extending from the first surface to the second surface electrically connects the second power electrode to an outer contact pad of the first metallization structure. A first epoxy layer arranged on side faces and on the first surface of the transistor device includes openings which define a lateral size of the plurality of outer contact pads and a package footprint.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.