Electrostatic discharge protection circuit for chip
US12088091B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 5, 2022 |
| Grant date | Sep 10, 2024 |
| Priority date | — |
| Expiry date | Jan 20, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02H1/0007
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
The present disclosure provides an electrostatic discharge (ESD) protection circuit for a chip, including: a monitoring unit, configured to generate a trigger signal when there is an ESD pulse on a power supply pad; a plurality of controllable drive units, connected to the monitoring unit, and each of the controllable drive units being configured to switch an operating state under a control of a control signal, wherein the operating state includes an output state, and the output state refers to generating a drive signal according to the trigger signal; and a discharge transistor, connected to the plurality of controllable drive units, and configured to be turned on under a drive of the drive signal so as to discharge an electrostatic charge to the ground pad.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.