Data bus signal conditioner and level shifter
US12088293B2 · kind B2 · utility
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3References
21Claims
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Key dates
| Filing date | Mar 21, 2022 |
| Grant date | Sep 10, 2024 |
| Priority date | — |
| Expiry date | Mar 21, 2042 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A circuit includes signal conditioner circuitry, level shifter circuitry, and state detector and controller circuitry coupled between the signal conditioner circuitry and the level shifter circuitry. The state detector and controller circuitry includes receiver circuitry and a finite state machine coupled to the receiver circuitry. The finite state machine is configured to detect a first data rate from signals, control operation of the signal conditioner circuitry responsive to detecting the first data rate, and control operation of the level shifter circuitry during a second data rate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.