Dynamic state management of a phase-lock loop (PLL)
US12088308B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 25, 2022 |
| Grant date | Sep 10, 2024 |
| Priority date | — |
| Expiry date | Nov 29, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0992
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase-lock loop (PLL) circuit provides continuous closed-loop operation when switching between operating modes, which may be selection between multiple oscillators, multiple power modes or frequency divider/multipliers of an local clock generator having one or more oscillator circuits, or other changes that may disrupt operation of the PLL. The PLL includes a loop filter having an input coupled to an output of a phase-frequency comparator that compares the output of the oscillator circuit to a reference and a control circuit for storing and restoring the complete state of the loop filter from the storage in response to a change of operating mode, so that a lock time of the phase-lock loop circuit is reduced when selection of one of the at least two selectable different output frequency ranges of the local clock generator is changed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.