Bitline settling and power supply rejection ratio in a nine cell pixel image sensor with phase detection autofocus
US12088937B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 8, 2022 |
| Grant date | Sep 10, 2024 |
| Priority date | — |
| Expiry date | Oct 13, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N25/75
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An imaging device includes a pixel array of pixel circuits arranged in rows and columns. Bitlines are coupled to the pixel circuits. Clamp circuits are coupled to the bitlines. Each of the clamp circuits includes a clamp short transistor to a power line and a respective one of the bitlines. The clamp short transistor is configured to be switched in response to a clamp short enable signal. A first diode drop device is coupled to the power line. A clamp idle transistor is coupled to the first diode drop device such that the first diode drop device and the clamp idle transistor are coupled between the power line and the respective one of the bitlines. The clamp idle transistor is configured to be switched in response to a clamp idle enable signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.