Layout for integrated resistor with current sense functionality
US12092664B2 · kind B2 · utility
0Cited by
8References
20Claims
0Family size
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Key dates
| Filing date | Jun 30, 2022 |
| Grant date | Sep 17, 2024 |
| Priority date | — |
| Expiry date | Mar 23, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R19/0092
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
One or more layout techniques may be used to balance a current sense circuit. The current sense circuit may include upstairs resistors for an amplifier which are formed of polysilicon material. The upstairs resistors may be arranged symmetrically about one or more stress gradients for improving an accuracy of the current sense circuit. The stress gradients may include stress gradients about an axis and stress gradients from a die edge.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.