Scan test in a single-wire bus circuit
US12092689B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 8, 2021 |
| Grant date | Sep 17, 2024 |
| Priority date | — |
| Expiry date | Apr 1, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5602
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A Scan test in a single-wire bus circuit is described in the present disclosure. The single-wire bus circuit has only one external pin for connecting to a single-wire bus. Given that multiple physical pins are required to carry out the Scan test, the single-wire bus circuit must provide additional pins required by the Scan test. In embodiments disclosed herein, the single-wire bus circuit includes a communication circuit under test, and a driver circuit coupled to the communication circuit via multiple internal pins. The driver circuit uses a subset of the internal pins as input pins and another subset of the internal pins as output pins to carry out the Scan test in the communication circuit. As a result, it is possible to perform the Scan test without adding additional external pins to the single-wire bus circuit, thus helping to reduce complexity and footprint of the single-wire bus circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.