Systems and methods for efficient error mitigation in quantum circuit execution using parity checks and classical feedback
US12093128B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 30, 2022 |
| Grant date | Sep 17, 2024 |
| Priority date | — |
| Expiry date | Dec 1, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods for efficient error mitigation in quantum circuit execution using parity checks and classical feedback are disclosed. A method may include a quantum computer: executing a quantum optimization algorithm comprising measurement points for measuring a quantum state parity, and termination instructions for stopping execution of the quantum optimization algorithm; preparing the quantum state; executing a first step of the quantum optimization algorithm; measuring a first parity of the quantum state; returning the first parity to a classical computer program; executing a second step of the quantum optimization algorithm; measuring a second parity of the quantum state; returning the second parity to the classical computer program that is configured to compare the first parity and the second parity; receiving an instruction to execute the termination instructions from the classical computer program in response to first parity and the second parity being different; and executing the termination instructions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.