Interface circuit, memory controller and method for calibrating signal processing devices in an interface circuit
US12093131B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 28, 2023 |
| Grant date | Sep 17, 2024 |
| Priority date | — |
| Expiry date | Jun 28, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/3062
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An interface circuit includes a signal processing circuit including multiple signal processing devices and a monitor and calibration module. The monitor and calibration module includes multiple monitor circuits, a processor and a calibration circuit. The monitor circuits monitor at least one of an amplitude, a frequency and a jitter in at least one of a reception signal and a transmission signal to correspondingly generate a monitored result and monitor at least one of power supplying voltage and ground voltage to correspondingly generate a monitored result. The processor collects the monitored results and determines a calibration operation based on the monitored results. The calibration circuit is coupled to the processor and at least one signal processing device and performs the calibration operation on the signal processing device to adjust a characteristic value of the signal processing device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.