Automated circuit generation
US12093619B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 8, 2023 |
| Grant date | Sep 17, 2024 |
| Priority date | — |
| Expiry date | May 8, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2111/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In some embodiments, information specifying a transistor to be generated is received, the information comprising an on resistance. A total width of a gate of the transistor to be generated is determined based at least on the on resistance. A first width, a number of fingers (F), and a number of device cells (P) are determined based on the total width. A transistor level schematic is generated comprising one or more transistors configured with the first width and the number of fingers (F). A layout is generated, wherein the layout comprises P device cells, each device cell comprising a plurality of gates corresponding to said number of fingers (F) each gate having said first width, wherein the device cells are configured in a two-dimensional array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.