Method for extracting parasitic capacitance of interconnection lines of integrated circuit based on discontinuous Galerkin finite element method
US12093633B1 · kind B1 · utility
Assignees
Inventors
Key dates
| Filing date | May 27, 2022 |
| Grant date | Sep 17, 2024 |
| Priority date | — |
| Expiry date | May 27, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2111/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure discloses a method for extracting parasitic capacitance of interconnection lines of an integrated circuit based on discontinuous Galerkin finite element method. The method includes: dividing non-uniform rectangular grids according to the distribution situation of conductors; determining whether the rectangular grids are boundary cell grids, and marking global numbers and numbers to be solved in sequence; initializing degree of freedom values of all rectangular grids; traversing all rectangular grids, obtaining a linear system of equations, and computing potential function degrees of freedom of all rectangular grids; obtaining an electric field strength function degree of freedom of each cell according to the potential function degree of freedom of each rectangular grid; and dividing a Gaussian surface of each conductor, performing integration of the determined electric field strength function on the Gaussian surface to obtain electric charge, and finally, obtaining main conductor capacitance and coupling capacitance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.