Fault code hierarchy system
US12094264B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 6, 2021 |
| Grant date | Sep 17, 2024 |
| Priority date | — |
| Expiry date | Aug 28, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG05B23/0275
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
An apparatus includes one or more processing circuits comprising one or more memory devices coupled to one or more processors, the one or more memory devices configured to store instructions thereon that, when executed by the one or more processors, cause the one or more processing circuits to perform various operations. The operations include wirelessly receiving a plurality of fault codes from a vehicle control system; prioritizing each fault code within the plurality of fault codes; determining a first root cause fault code corresponding to the highest prioritized fault code in the plurality of fault codes; determining a first set of interaction fault codes, the first set of interaction fault codes relating to the first root cause fault code based on a causal relationship; and wirelessly transmitting the first root cause fault code and the first set of interaction fault codes to a display of an interface device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.