Display panel and display device with reduced charge accumulation in semiconductor layer
US12094384B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Jun 1, 2023 |
| Grant date | Sep 17, 2024 |
| Priority date | — |
| Expiry date | Jun 1, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/60
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A display panel has a display region and a frame region outside the display region. The display region includes a plurality of pixel circuits. The display panel includes a base substrate, a buffer layer, a semiconductor layer, a power signal layer, and an auxiliary circuit layer. The buffer layer is on a side of the base substrate. The buffer layer includes an a-Si layer. The semiconductor layer is on a side of the buffer layer away from the base substrate. The power signal layer is on a side of the semiconductor layer away from the base substrate. The power signal layer includes a plurality of first power voltage lines in the display region, and one first power voltage line of the plurality of first power voltage lines are electrically connected to a corresponding pixel circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.