Patent · US Active

Computation in-memory using 6-transistor bit cells

US12094524B2 · kind B2 · utility

0Cited by

1References

18Claims

0Family size

Assignee

TEXAS INSTRUMENTS INCORPORATED · US

Inventors

Avishek Biswas · Dallas, US
Mahesh M. Mehendale · Bengaluru, IN
Hetul Sanghvi · Bengaluru, IN

Key dates

Filing date	Jan 29, 2021
Grant date	Sep 17, 2024
Priority date	—
Expiry date	Jul 8, 2043

Classification

Technology area (CPC G)Physics
CPC primaryG11C11/54
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A device includes a bit cell having first and second terminals, a first bit line coupled to the first terminal, a second bit line coupled to the second terminal, a first capacitor, a second capacitor, and a multiply and average (MAV) circuit coupled to the first capacitor, to the second capacitor, to the first bit line, and to the second bit line. The MAV circuit includes a first transistor coupled to the first capacitor and to a ground terminal and a second transistor coupled to the second capacitor and to the ground terminal. The first transistor has a first transistor control terminal selectively coupled to the first bit line and the second transistor has a second transistor control terminal selectively coupled to the second bit line.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.