Array substrate
US12094888B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 5, 2021 |
| Grant date | Sep 17, 2024 |
| Priority date | — |
| Expiry date | Jan 5, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/443
Abstract
An array substrate includes a substrate, a first metal layer and an active layer disposed on the substrate, an interlayer insulating layer, and a second metal layer. The first metal layer forms at least one first trace, the interlayer insulating layer is disposed on the first metal layer and the active layer, the second metal layer is disposed on the interlayer insulating layer, the interlayer insulating layer is formed with a first contact hole, and the second metal layer is connected to the first trace through the first contact hole. The first metal layer includes a conductive layer and a first protective layer stacked in sequence.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.