Self calibrating barrier modulation pixel
US12096140B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Aug 10, 2022 |
| Grant date | Sep 17, 2024 |
| Priority date | — |
| Expiry date | Jan 29, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F39/8037
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
In an embodiment a pixel arrangement includes a photodetector configured to accumulate charge carriers by converting electromagnetic radiation, a transfer transistor electrically coupled to the photodetector, a diffusion node electrically coupled to the transfer transistor, a reset transistor electrically coupled to the diffusion node and to a pixel supply voltage and a sample-and-hold stage including at least a first capacitor and a second capacitor, an input of the sample-and-hold stage being electrically coupled to the diffusion node via an amplifier, wherein the transfer transistor is configured to be pulsed to different voltage levels for transferring parts of the accumulated charge carriers to the diffusion node, wherein at least the second capacitor is configured to store a low conversion gain signal representing a first part of the accumulated charge carriers, and wherein the first capacitor is configured to store a high conversion gain signal representing a remaining part of the accumulated charge carriers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.