Semiconductor structure and manufacturing method thereof

US12096616B2 · kind B2 · utility

Assignee

• CHANGXIN MEMORY TECHNOLOGIES, INC. · CN

Inventors

• Ming-Da Cheng · Zhubei City, TW
• Xing Jin · Beijing, CN
• Ran Li · Beijing, CN

Key dates

• Filing date: Jul 30, 2021
• Grant date: Sep 17, 2024
• Expiry date: Dec 8, 2042

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/315

Abstract

An embodiment of the disclosure provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a substrate, a bit line structure located on the substrate, a capacitor contact hole located on two opposite sides of the bit line structure, and an isolation sidewall. The isolation sidewall is located between the bit line structure and the capacitor contact hole. A gap is provided between the isolation sidewalls located on the two opposite sides of the bit line structure. The gap is located on the bit line structure.