Semiconductor structure and manufacturing method thereof

US12096619B2 · kind B2 · utility

Assignee

• CHANGXIN MEMORY TECHNOLOGIES, INC. · CN

Inventors

• Youming Liu · Longbeilingcun, CN
• Deyuan Xiao · Shanghai, CN

Key dates

• Filing date: Aug 1, 2022
• Grant date: Sep 17, 2024
• Expiry date: Mar 30, 2043

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/488

Abstract

The present disclosure provides a semiconductor structure and a manufacturing method thereof, and relates to the technical field of semiconductors, including: a substrate, a first stacked structure is disposed on the substrate, and the first stacked structure includes a memory cell array; a plurality of word lines (WLs), where the WL is disposed in the first stacked structure and is electrically connected to the memory cell array; a plurality of bit lines (BLs), the BL is disposed beside the first stacked structure, and is electrically connected to the memory cell array; and one end of each BL away from the memory cell array forms a step, and the BL includes a first core layer and a first conductive layer covering the first core layer; and a plurality of BL plugs, each BL plug is in corresponding contact with the first conductive layer of one of the BLs.