Clock skew-adjustable chip clock architecture of programmable logic chip
US12099377B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 29, 2022 |
| Grant date | Sep 24, 2024 |
| Priority date | — |
| Expiry date | Mar 15, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/34
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A delay adjustment cell is disposed in a channel of at least one regional clock of a chip clock architecture, and the delay adjustment cell includes a plurality of parallel delay paths with different delay values. The delay adjustment cell gates one of the delay paths based on an obtained configuration signal such that a connected regional clock has a corresponding target delay, and a target delay of each regional clock corresponds to a clock skew mode of the programmable logic chip. A clock skew between different regional clocks is adjusted by controlling the gated delay path in the delay adjustment cell, such that a clock skew of the chip can be adjusted in a relatively large range. Under the same resource configuration, different path choices of the delay adjustment cell lead to different clock skews to meet different clock skew modes in different application scenarios.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.