Memory striping approach that interleaves sub protected data words
US12099408B2 · kind B2 · utility
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2References
14Claims
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Key dates
| Filing date | Dec 23, 2020 |
| Grant date | Sep 24, 2024 |
| Priority date | — |
| Expiry date | Jan 9, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7208
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus is described. The apparatus includes a memory controller having logic circuitry to write a unit of write data into a plurality of memory chips according to a striping pattern that includes multiple protected sub words, each protected sub word including a smaller portion of the unit of write data and error correction coding (ECC) information calculated from the smaller portion of the unit of write data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.