Memory controller, information processing apparatus, and information processing method
US12099413B2 · kind B2 · utility
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6Claims
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Key dates
| Filing date | Jan 26, 2023 |
| Grant date | Sep 24, 2024 |
| Priority date | — |
| Expiry date | Apr 5, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1621
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory controller includes a request pipeline and a retry control circuit. The request pipeline receives an input of a request to a memory output from a processor core, stores the request, and causes the memory to process the request in order of storage. The retry control circuit stops a new request input to the request pipeline when an error occurs in the memory, and re-inputs, to the request pipeline, requests to be retried that includes the request in which the error has occurred and a subsequent request stored in the request pipeline.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.