Virtually-indexed cache coherency using physical address proxies
US12099448B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 24, 2022 |
| Grant date | Sep 24, 2024 |
| Priority date | — |
| Expiry date | Feb 23, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/151
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A cache memory subsystem includes virtually-indexed L1 and PIPT L2 set-associative caches having an inclusive allocation policy such that: when a first copy of a memory line specified by a physical memory line address (PMLA) is allocated into an L1 entry, a second copy of the line is also allocated into an L2 entry; when the second copy is evicted, the first copy is also evicted. For each value of the PMLA, the second copy can be allocated into only one L2 set, and an associated physical address proxy (PAP) for the PMLA includes a set index and way number that uniquely identifies the entry. For each value of the PMLA there exist two or more different L1 sets into which the first copy can be allocated, and when the L2 evicts the second copy, the L1 uses the PAP of the PMLA to evict the first copy.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.