Application partitioning for locality in a stacked memory system
US12099453B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 30, 2022 |
| Grant date | Sep 24, 2024 |
| Priority date | — |
| Expiry date | Sep 29, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1006
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present disclosure relate to application partitioning for locality in a stacked memory system. In an embodiment, one or more memory dies are stacked on the processor die. The processor die includes multiple processing tiles and each memory die includes multiple memory tiles. Vertically aligned memory tiles are directly coupled to and comprise the local memory block for a corresponding processing tile. An application program that operates on dense multi-dimensional arrays (matrices) may partition the dense arrays into sub-arrays associated with program tiles. Each program tile is executed by a processing tile using the processing tile's local memory block to process the associated sub-array. Data associated with each sub-array is stored in a local memory block and the processing tile corresponding to the local memory block executes the program tile to process the sub-array data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.