Power efficient display architecture
US12100335B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 17, 2022 |
| Grant date | Sep 24, 2024 |
| Priority date | — |
| Expiry date | Nov 17, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2370/16
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
This disclosure provides systems, devices, apparatus, and methods, including computer programs encoded on storage media, for a power efficient display architecture. A display processor may obtain an indication that UC is to be displayed at a first resolution or a second resolution, where the first resolution is higher than the second resolution. The display processor may drive a first display via a first controller of a first DPU based on the indication. The display processor may drive a second display via a controller of a second DPU if the UC is to be displayed at the first resolution, or drive the second display via a second controller of the first DPU if the UC is to be displayed at the second resolution.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.