Readout circuit layout and sense amplification circuit
US12100441B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 9, 2022 |
| Grant date | Sep 24, 2024 |
| Priority date | — |
| Expiry date | Feb 14, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A readout circuit architecture and a sense amplification circuit are provided. The readout circuit architecture includes: a readout amplification unit including a first P-type transistor and a second P-type transistor; and a first offset compensation unit including a first offset compensation transistor and a second offset compensation transistor. The first P-type transistor is arranged in a first area and the second P-type transistor is arranged in a second area. When the first area and the second area are arranged at interval in a first direction, the first offset compensation transistor and the second offset compensation transistor are arranged in a third area located between the first area and the second area. When the first area and the second area are arranged adjacently in the first direction, the first offset compensation transistor is arranged in a fourth area and the second offset compensation transistor is arranged in a fifth area.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.