Clock qualifier enhancement for external double data rate memory interfaces
US12100474B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 28, 2022 |
| Grant date | Sep 24, 2024 |
| Priority date | — |
| Expiry date | Apr 27, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4243
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory interface circuit has a first differential receiver having a first input coupled to a first reference voltage source, a second differential receiver configured to receive a differential data strobe signal in a pair of complementary signals, a third differential receiver having a first input coupled to a second reference voltage source and a second input configured to receive one of the pair of complementary signals, a clock generation circuit configured to generate a read clock signal based on an output of the second differential receiver and using a qualifying signal output by the third differential receiver to qualify one or more edges in the read clock signal and a data capture circuit clocked by the read clock signal and configured to capture data from the output of the first differential receiver using the one or more edges in the read clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.