High-performance capacitor packaging for next generation power electronics
US12100560B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 12, 2022 |
| Grant date | Sep 24, 2024 |
| Priority date | — |
| Expiry date | Apr 5, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/10636
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A capacitor packaging having a central termination and three or more capacitors (or groups of capacitors) arranged about the central termination. The electrical flow paths between the termination and the capacitors or groups of capacitors are of substantially the same length. The capacitors or groups of capacitors may be arranged in a generally circular pattern with the termination centered on the center. The termination may include first and second terminals. The capacitors may be mounted to a printed circuit board (“PCB”) with traces on opposite surfaces of the PCB providing electrical flow paths from the terminals to opposite legs of the capacitors. The capacitor packaging may include a primary PCB with a first circular arrangement of capacitors and a secondary PCB with a second circular arrangement of capacitors. The capacitors may be sandwiched between the PCBs with the second arrangement of capacitors disposed concentrically inwardly of the first arrangement.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.