Semiconductor structure and method for forming semiconductor structure, stacked structure, and wafer stacking method
US12100677B2 · kind B2 · utility
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Key dates
| Filing date | Apr 28, 2022 |
| Grant date | Sep 24, 2024 |
| Priority date | — |
| Expiry date | Oct 21, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/35121
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor structure, a method for forming a semiconductor structure, a stacked structure, and a wafer stacking method are provided. The semiconductor structure includes: a semiconductor substrate; a first dielectric layer on a surface of a semiconductor substrate; a top metal layer, in which the top metal layer is located in the first dielectric layer, and the top metal layer penetrates through the first dielectric layer; and a buffer layer located between the top metal layer and the first dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.