Semiconductor arrangement and method of making
US12100754B2 · kind B2 · utility
1Cited by
2References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Mar 29, 2021 |
| Grant date | Sep 24, 2024 |
| Priority date | — |
| Expiry date | Aug 23, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/141
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor arrangement includes a first well formed to a first depth and a first width in a substrate and a second well formed to a second depth and a second width in the substrate. The first well is formed in the second well, the first depth is greater than the second depth, and the second width is greater than the first width. A source region is formed in the second well and a drain region is formed in the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.