Decoupling capacitor circuits
US12101091B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 25, 2023 |
| Grant date | Sep 24, 2024 |
| Priority date | — |
| Expiry date | Apr 25, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/692
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method includes fabricating a first transistor and a second transistor on a substrate and fabricating a first conducting line and a second conducting line in a first metal layer. The method also includes connecting a gate of the first transistor to the first conducting line and connecting a gate of the second transistor to the second conducting line. The first conducting line and the second conducting line are parallel and adjacent to each other in the first metal layer above the first transistor and the second transistor. The method still includes connecting a source and a drain of the first transistor to a third conducting line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.