Synchronizing systems on a chip using a shared clock
US12105553B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 22, 2023 |
| Grant date | Oct 1, 2024 |
| Priority date | — |
| Expiry date | Aug 22, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2213/0026
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An electronic eyewear device includes first and second systems on a chip (SoCs) having independent time bases that are synchronized by generating a common clock signal from a clock generator of the first SoC and simultaneously applying the common clock signal to a first counter of the first SoC and a second counter of the second SoC whereby the first counter and the second counter count clock edges of the common clock. The clock counts are shared through an interface between the first SoC and the second SoC and compared to each other. When the clock counts are different, a clock count of the first counter or the second counter is adjusted to cause the clock counts to match each other. The adjusted clock count is synchronized to the respective clocks of the first and second SoCs, thus synchronizing the first and second SoCs to each other.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.