Method and apparatus for vector permutation
US12105635B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 26, 2021 |
| Grant date | Oct 1, 2024 |
| Priority date | — |
| Expiry date | Mar 12, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H2017/0298
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method is provided that includes performing, by a processor in response to a vector permutation instruction, permutation of values stored in lanes of a vector to generate a permuted vector, wherein the permutation is responsive to a control storage location storing permute control input for each lane of the permuted vector, wherein the permute control input corresponding to each lane of the permuted vector indicates a value to be stored in the lane of the permuted vector, wherein the permute control input for at least one lane of the permuted vector indicates a value of a selected lane of the vector is to be stored in the at least one lane, and storing the permuted vector in a storage location indicated by an operand of the vector permutation instruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.