Devices, chips, and electronic equipment for computing-in-memory
US12105986B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 9, 2022 |
| Grant date | Oct 1, 2024 |
| Priority date | — |
| Expiry date | Dec 6, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/405
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computing-in-memory array, chip and electronic device includes a computing-in-memory array including at least one computing-in-memory cell having a first switch, a second switch, a third switch, a fourth switch, a coupling capacitor, a first bitline, a second bitline, a third bitline, a first wordline, a second wordline and a third wordline; a control module connected to the computing-in-memory array, which controls the voltages of each wordline and bitline to read and write data through the computing-in-memory array, or to perform computing-in-memory operations. By arranging the first switch, the second switch, the third switch, and the fourth switch in a differential form, and determining the stored value by the difference of the voltage between the two ports of the second switch and the third switch, the present embodiment of the disclosure can implement computing-in-memory operations with high accuracy, low circuit complexity, high reliability, and high energy efficiency. For memory function, the computing-in-memory device has a long data retention time and low data refresh overhead.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.